文献类型：会议论文

英文题名：Scanline-based fast algorithm and pipelined hardware design of rate-distortion optimized quantization for AVS3

作者：Zhao, Jiachen[1,3];Yang, Fan[2];Huang, Xiaofeng[3,4];Xiang, Gwoqing[2,3];Zhang, Peng[3];Zhao, Liping[5];Yan, Wei[1]

机构：[1]Peking Univ, Sch Software & Microelect, Beijing, Peoples R China;[2]Peking Univ, Sch Comp Sci, Beijing, Peoples R China;[3]Peking Univ, Adv Inst Informat Technol, Hangzhou, Peoples R China;[4]Hangzhou Dianzi Univ, Sch Commun Engn, Hangzhou, Peoples R China;[5]Shaoxing Univ, Dept Comp Sci & Engn, Shaoxing, Peoples R China

会议论文集：IEEE International Conference on Consumer Electronics (ICCE)

会议日期：JAN 06-08, 2023

会议地点：Las Vegas, NV

语种：英文

外文关键词：AVS3; rate-distortion optimized quantization (RDOQ); zig-zag; parallel optimization; video coding

外文摘要：The third generation AVS video coding standard (AVS3) is developed by the China AVS working group, and it achieves a 50% bitrate saving compared to the previous AVS2 standard by adopting several efficient coding tools. Ratedistortion optimized quantization (RDOQ) is one of the effective tools, which decides the optimal quantized coefficient level based on rate-distortion cost. The huge computation complexity and strong data dependency in RDOQ impede the realtime applications, where there is no hardware video encoder supporting RDOQ. To resolve this problem, we propose a zigzag scanline-based fast algorithm and pipelined hardware design for AVS3 RDOQ. Firstly, we introduce an approach to decrease computation and then propose a fully parallel coefficient level decision method where the context is correlated to the current position. Secondly, a zig-zag scanline-based algorithm is proposed to decide the last non-zero pixel position, where the scanlines can be paralleled. Finally, its corresponding hardware architecture design is proposed. Experimental results show that the proposed hardware architecture can support a throughput of 4K@30fps with negligible performance loss when working at 200MHz.