文献类型：会议论文

英文题名：Architecture Design of AVS3 Fractional Motion Estimation for 4K UHD Video Coding

作者：Tong, Sikai[1,3];Zeng, Yuning[1];Xiang, Guoqing[2,3];Huang, Xiaofeng[3,4];Zhang, Peng[3];Zhao, Liping[5];Yan, Wei[1]

机构：[1]Peking Univ, Sch Software & Microelect, Beijing, Peoples R China;[2]Peking Univ, Sch Comp Sci, Beijing, Peoples R China;[3]Peking Univ, Adv Inst Informat Technol, Hangzhou, Peoples R China;[4]Hangzhou Dianzi Univ, Sch Commun Engn, Hangzhou, Peoples R China;[5]Shaoxing Univ, Dept Comp Sci & Engn, Shaoxing, Peoples R China

会议论文集：IEEE International Conference on Consumer Electronics (ICCE)

会议日期：JAN 06-08, 2023

会议地点：Las Vegas, NV

语种：英文

外文关键词：Parallel; Pipeline; Fractional pixel motion estimation; Fractional pixel motion estimation architecture

外文摘要：The third generation of video coding standards (AVS3) has significantly improved video coding performance. It adopts three block division mechanisms, including Binary-Tree (BT) division, Quad-Tree (QT) division and extended Quad-Tree (EQT) division. These three block division increase the computation amount of fractional pixel motion estimation (FME), making it difficult to implement a real-time FME hardware. This paper proposes a 17-point fractional pixel parallel search algorithm and small-sized motion vector substitution(MVS) algorithm to reduce the number of CUs for FME. Combined with these two hardware friendly algorithms, we design a parallel pipeline architecture suitable for CUs with sizes from 4x4 to 64x64. FME hardware module is divided into four circuits to process CUs of different sizes. Each circuit is divided into eight flow modules to ensure that the clock cycles required by each circuit are almost the same. These eight flow modules include data preparation, interpolation, search, rate-distortion optimization (RDO) and other modules to calculate fractional pixel motion vector (FMV) of CUs. MVS module uses the deduced FMVs to substitute FMV of the remaining CUs. Experimental results show that the proposed algorithms have 0.28% performance degradation in BD-Rate. The parallel pipeline architecture supports real-time encoding of 3840x2160@60fps.